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functional block diagram sar and adc control charge redistribution dac buf 2.5v reference t/h i/p mux comp calibration memory and controller serial interface/control register ad7858/ ad7858l av dd agnd ain1 ain8 ref in /ref out c ref1 c ref2 cal sync din dout sclk dv dd dgnd clkin convst busy sleep rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 3 v to 5 v single supply, 200 ksps 8-channel, 12-bit sampling adc ad7858/ad7858l features specified for v dd of 3 v to 5.5 v ad7858200 ksps; ad7858l100 ksps system and self-calibration with autocalibration on power-up eight single-ended or four pseudo-differential inputs low power ad7858: 12 mw (v dd = 3 v) ad7858l: 4.5 mw (v dd = 3 v) automatic power-down after conversion (25 w) flexible serial interface: 8051/spi?/qspi?/ p compatible 24-lead dip, soic, and ssop packages applications battery-powered systems (personal digital assistants, medical instruments, mobile communications) pen computers instrumentation and control systems high-speed modems general description the ad7858/ad7858l are high-speed, low-power, 12-bit adcs that operate from a single 3 v or 5 v power supply, the ad7858 being optimized for speed and the ad7858l for low power. the adc powers up with a set of default conditions at which time it can be operated as a read-only adc. the adc contains self-calibration and system calibration options to en- sure accurate operation over time and temperature and have a number of power-down options for low-power applications. the part powers up with a set of default conditions and can operate as a read-only adc. the ad7858 is capable of 200 khz throughput rate while the ad7858l is capable of 100 khz throughput rate. the input track-and-hold acquires a signal in 500 ns and features a pseudo-differential sampling scheme. the ad7858/ad7858l voltage range is 0 to v ref with straight binary output coding. input signal range is to the supply and the part is capable of con- verting full power signals to 100 khz. cmos construction ensures low power dissipation of typically 4.5 mw for normal operation and 1.15 mw in power-down mode with a throughput rate of 10 ksps (v dd = 3 v). the part is available in 24-lead, 0.3 inch-wide dual-in-line package (dip), 24-lead small outline (soic), and 24-lead small shrink outline (ssop) packages. see page 31 for data sheet index. spi and qspi are trademarks of motorola, inc. product highlights 1. specified for 3 v and 5 v supplies. 2. automatic calibration on power-up. 3. flexible power management options including automatic power-down after conversion. 4. operates with reference voltages from 1.2 v to v dd . 5. analog input range from 0 v to v dd . 6. eight single-ended or four pseudo-differential input channels. 7. system and self-calibration. 8. versatile serial i/o port (spi/qspi/8051/ p). 9. lower power version ad7858l. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000
p arameter a version 1 b version 1 units test conditions/comments dynamic performance signal to noise + distortion ratio 3 70 71 db min typically snr is 72 db (snr) v in = 10 khz sine wave, f sample = 200 khz (100 khz) total harmonic distortion (thd) e78 e78 db max v in = 10 khz sine wave, f sample = 200 khz (100 khz) peak harmonic or spurious noise e78 e78 db max v in = 10 khz sine wave, f sample = 200 khz (100 khz) intermodulation distortion (imd) second order terms e78 e80 db typ fa = 9. 983 khz, fb = 10.05 khz, f sample = 200 khz (100 khz) third order terms e78 e80 db typ fa = 9. 983 khz, fb = 10.05 khz, f sample = 200 khz (100 khz) channel-to-channel isolation e90 e90 db typ v in = 25 khz dc accuracy any channel resolution 12 12 bits integral nonlinearity 1 1 lsb max 2.5 v external r eference v dd = 3 v, v dd = 5 v (b grade only) 1 0.5 lsb max 5 v external reference v dd = 5 v ( 1) lsb max (l version, 5 v external reference, v dd = 5 v) ( 1) lsb max (l version) differential nonlinearity 1 1 lsb max guaranteed no missed codes to 12 bits. 2.5 v external reference v dd = 3 v, 5 v external reference, v dd = 5 v total unadjusted error 1 1 lsb typ unipolar offset error 5 5 lsb max typically 2 lsbs 2.5 2.5 lsb max 5 v external reference, v dd = 5 v ( 3) ( 3) lsb max (l version) ( 1.5) ( 1.5) lsb max (l version, 5 v external reference, v dd = 5 v) unipolar offset error match 1.5 1.5 lsb max positive full-scale error 4 4 lsb max 1.5 1.5 lsb max 5 v external refere nce, v dd = 5 v positive full-scale error match 1 1 lsb max analog input input voltage ranges 0 to v ref 0 to v ref volts i.e., ain(+) e ain(e) = 0 to v ref , ain(e) can be biased up but ain(+) cannot go below ain(e) leakage current 1 1 a max input capacitance 20 20 pf typ reference input/output ref in input voltage range 2.3/v dd 2.3/v dd v min/max functional from 1.2 v input impedance 150 150 k typ ref out output voltage 2.3/2.7 2.3/2.7 v min/max ref out tempco 20 20 ppm/ c typ logic inputs input high voltage, v inh 2.4 2.4 v min av dd = dv dd = 4.5 v to 5.5 v 2.1 2.1 v min av dd = dv dd = 3.0 v to 3.6 v input low voltage, v inl 0.8 0.8 v max av dd = dv dd = 4.5 v to 5.5 v 0.6 0.6 v max av dd = dv dd = 3.0 v to 3.6 v input current, i in 10 10 a max typically 10 na, v in = 0 v or v dd input capacitance, c in 4 10 10 pf max logic outputs output high voltage, v oh i source = 200 a 4 4 v min av dd = dv dd = 4.5 v to 5.5 v 2.4 2.4 v min av dd = dv dd = 3.0 v to 3.6 v output low voltage, v ol 0.4 0.4 v max i sink = 0.8 ma floating-state leakage current 10 10 a max floating-state output capacitance 4 10 10 pf max output coding straight (natural) binary conversion rate conversion time 4.6 (18) 4.6 s max (l versions only, e40 c to +85 c, 1 mhz clkin) (10) s max (l versions only, 0 c to +70 c, 1.8 mhz clkin) track/hold acquisition time 0.4 (1) 0.4 (1) s min (l versions only) "#" ad7858/ad7858lespecifications 1, 2 (av dd = dv dd = +3.0 v to +5.5 v, ref in /ref out = 2.5 v external reference unless otherwise noted, f clkin = 4 mhz (1.8 mhz b grade (0 c to +70 c), 1 mhz a and b grades (e40 c to +85 c) for l version); f sample = 200 khz (ad7858), 100 khz (ad7858l); sleep
parameter a version 1 b version 1 units test conditions/comments dynamic performance av dd, dv dd +3.0/+5.5 +3.0/+5.5 v min/max i dd normal mode 5 6 (1.9) 6 (1.9) ma max av dd = dv dd = 4.5 v to 5.5 v. typically 4.5 ma (1.5) 5.5 (1.9) 5.5 (1.9) ma max av dd = dv dd = 3.0 v to 3.6 v. typically 4.0 ma (1.5 ma) sleep mode 6 with external clock on 10 10 a typ full power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 0 400 400 a typ partial power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 1 with external clock off 5 5 a max typically 1 a. full power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 0 200 200 a typ partial power-down. power management bits in control register set as pmgt1 = 1, pmgt0 = 1 normal-mode power dissipation 33 (10.5) 33 (10.5) mw max v dd = 5.5 v. typically 25 mw (8); sleep sleep s sleep s sleep s s sleep s s sleep c c c c p p p p p p p convst sleep cal sync convst sleep cal sync l c l c slep3c
"%" ad7858/ad7858l limit at t min , t max (a, b versions) parameter 5 v 3 v units description f clkin 2 500 500 khz min master clock frequency 4 4 mhz max 1.8 1.8 mhz max l version, 0 c to +70 c, b grade only 1 1 mhz max l version, e40 c to +85 c f sclk 4 4 mhz max t 1 3 100 100 ns min convst convst o n s s sync o o 0.4 t sclk 0.4 t sclk ns min/max sync o o sync o sync o o n n sync n sync n n n cal n n convst o n p convst convst
ad7858/ad7858l "&" typical timing diagrams figures 2 and 3 show typical read and write timing diagrams for serial interface mode 2. the reading and writing occurs after conversion in figure 2, and during conversion in figure 3. to attain the maximum sample rate of 100 khz (ad7858l) or 200 khz (ad7858), reading and writing must be performed during conversion as in figure 3. at least 400 ns acquisition time must be allowed (the time from the falling edge of busy to the next rising edge of convst convst s 33333333fha3p td3fahfi3vta3ffid3hihi3fyfn 3fvfdiftnz s s snovpt pcos fha3p 3fyfn3fdady3vta3oniavd3t33sdfnafifn3via3tnazftn s s snovpt pcos fha3p 3fyfn3fdady3vta3oniavd3t33sdfnafifn3hafn3tnazftn
"5" ad7858/ad7858l ordering guide linearity power error dissipation package model (lsb) 1 (mw) options 2 ad7858an 1 20 n-24 ad7858bn 1/2 20 n-24 ad7858lan 3 1 6.85 n-24 ad7858lbn 3 1 6.85 n-24 ad7858ar 1 20 r-24 ad7858br 1/2 20 r-24 ad7858lar 3 1 6.85 r-24 ad7858lbr 3 1 6.85 r-24 ad7858lars 3 1 6.85 rs-24 eval-ad7858cb 4 eval-control board 5 notes 1 linearity error here refers to integral linearity error. 2 n = plastic dip; r = soic; rs = ssop. 3 l signifies the low-power version. 4 this can be used as a stand-alone evaluation board or in conjunction with the eval- control board for evaluation/demonstration purposes. 5 this board is a complete unit allowing a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. absolute maximum ratings 1 (t a = +25 c unless otherwise noted) av dd to agnd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v dv dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +7 v av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . . e0.3 v to +0.3 v analog input voltage to agnd . . . . e0.3 v to av dd + 0.3 v digital input voltage to dgnd . . . . e0.3 v to dv dd + 0.3 v digital output voltage to dgnd . . . e0.3 v to dv dd + 0.3 v ref in /ref out to agnd . . . . . . . . . e0.3 v to av dd + 0.3 v input current to any pin except supplies 2 . . . . . . . 10 ma operating temperature range commercial (a, b versions) . . . . . . . . . . . e40 c to +85 c storage temperature range . . . . . . . . . . . e65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c plastic dip package, power dissipation . . . . . . . . . . 450 mw ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 105 c/w jc thermal impedance . . . . . . . . . . . . . . . . . . . . 34.7 c/w lead temperature, (soldering, 10 sec) . . . . . . . . . . +260 c soic, ssop package, power dissipation . . . . . . . . . . 450 mw ja thermal impedance . . . 75 c/w (soic) 115 c/w (ssop) jc thermal impedance . . . . 25 c/w (soic) 35 c/w (ssop) lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up. pin configurations dip, soic, and ssop 13 16 15 14 24 23 22 21 20 19 18 17 top view (not to scale) 12 11 10 9 8 1 2 3 4 7 6 5 ad7858/ ad7858l din clkin sclk busy
ref in /ref out dv dd dgnd dout av dd agnd c ref1 c ref2 ain1 ain2 ain7 ain8 ain3 ain4 ain6 ain5 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7858/ad7858l features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
ad7858/ad7858l "." pin function descriptions pin mnemonic description 1 convst convst cal sleep s s cal s sync
"/" ad7858/ad7858l terminology 1 integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the end- points of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. total unadjusted error this is the deviation of the actual code from the ideal code tak- ing all errors into account ( gain, offset, integral nonlinearity, and other errors ) at any point along the transfer function. unipolar offset error this is the deviation of the first code transition (00 . . . 000 to 00 . . . 001) from the ideal ain(+) voltage (ain(? + 1/2 lsb). positive full-scale error this is the deviation of the last code transition from the ideal ain(+) voltage (ain(? + full scale ?1.5 lsb) after the offset error has been adjusted out. channel-to-channel isolation channel-to-channel isolation is a measure of crosstalk between the channels. it is measured by applying a full-scale 25 khz signal to the other seven channels and determining how much that signal is attenuated in the channel of interest. the figure given is the worst case for all channels. track/hold acquisition time the track/hold amplifier returns into track mode and the end of conversion. track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within 1/2 lsb, after the end of conversion. signal to (noise + distortion) ratio this is the measured ratio of signal to (noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitiza- tion process; the more levels, the smaller the quantization noise. the theoretical signal to (noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal to (noise + distortion) = (6.02 n +1.76) db thus for a 12-bit converter, this is 74 db. 1 ain(+) refers to the positive input of the pseudo differential pair, and ain(? refers to the negative analog input of the pseudo differential pair or to agnd depending on the channel configuration. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the ad7858/ad7858l, it is defined as: thd db
20 log ( v 2 2 v 3 2 v 4 2 v 5 2 v 6 2 ) v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation distortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa fb), while the third order terms include (2fa + fb), (2fa fb), (fa + 2fb), and (fa 2fb). testing is performed using the ccif standard where two input frequencies near the top end of the input bandwidth are used. in this case, the second order terms are usually distanced in fre- quency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dbs.
ad7858/ad7858l "6" on-chip registers the ad7858/ad7858l powers up with a set of default conditions. the only writing required is to select the channel configuration . without performing any other write operations the ad7858/ad7858l still retains the flexibility for performing a full power-down and a full self-calibration. extra features and flexibility, such as performing different power-down options, different types of calibrations including syst em calibration, and software conversion start, can be selected by further writing to the part. the ad7858/ad7858l contains a control register , adc output data register , status register , test register, and 10 calibration registers . the control register is write-only, the adc output data register and the status register are read-only, and the test and calibration r egisters are both read/write registers. the t est register is used for testing the part and should not be written to. addressing the on-chip registers writing a write operation to the ad7858/ad7858l consists of 16 bits. the two msbs, addr0 and addr1, are decoded to determine which register is addressed, and the subsequent 14 bits of data are written to the addressed register. it is not until all 16 b its are written that the data is latched into the addressed registers. table i shows the decoding of the address bits while figure 4 sh ows the overall write register hierarchy. table i. write register addressing addr1 addr0 comment 0 0 this combination does not address any register so the subsequent 14 data bits are ignored. 0 1 this combination addresses the test register . the subsequent 14 data bits are written to the test register. 1 0 this combination addresses the calibration registers . the subsequent 14 data bits are written to the selected calibration register. 1 1 this combination addresses the control register . the subsequent 14 data bits are written to the control register. reading to read from the various registers the user must first write to bits 6 and 7 in the control register, rdslt0 and rdslt1. these bits are decoded to determine which register is addressed during a read operation. table ii shows the decoding of the read addr ess bits while figure 5 shows the overall read register hierarchy. the power-up status of these bits is 00 so that the default read will be from the adc output data register. once the read selection bits are set in the control register, all subsequent read operations that follow will be from the selec ted regis- ter until the read selection bits are changed in the control register. table ii. read register addressing rdslt1 rdslt0 comment 0 0 all successive read operations will be from adc output data register . this is the power-up default setting. there will always be 4 leading zeros when reading from the adc output data register. 0 1 all successive read operations will be from test register . 1 0 all successive read operations will be from calibration registers. 1 1 all successive read operations will be from status register . 01 10 11 00 01 10 11 addr1, addr0 decode test register control register gain(1) offset(1) dac(8) gain(1) offset(1) offset(1) gain(1) calibration registers calslt1, calslt0 decode '% 30 01 10 11 00 01 10 11 rdslt1, rdslt0 decode test register status register gain(1) offset(1) dac(8) gain(1) offset(1) offset(1) gain(1) calibration registers calslt1, calslt0 decode 00 adc output data register '& 0
"(7" ad7858/ad7858l control register the arrangement of the control register is shown below. the control register is a write only register and contains 14 bits of d ata. the control register is selected by putting two 1s in addr1 and addr0. the function of the bits in the control register are de- scribed below. the power-up status of all bits is 0. msb sgl/ diff ch2 ch1 ch0 pmgt1 pmgt0 rdslt1 rdslt0 2/ 3 mode convst calmd calslt1 calslt0 stcal lsb control register bit function description bit mnemonic comment 13 sgl/ diff a 0 in this bit position configures the input channels in pseudo-differential mode. a 1 in this bit position configures the input channels in single-ended mode (see table iii). 12 ch2 these three bits are used to select the channel on which the conversion is performed. the channels can 11 ch1 be configured as eight single-ended channels or four pseudo-differential channels. the default selection 10 ch0 is ain1 for the positive input and ain2 for the negative input (see table iii for channel selection). 9 pmgt1 power management bits. these two bits are used with the sleep pin for putting the part into various 8 pmgt0 power-down modes (see power-down section for more details). 7 rdslt1 theses two bits determine which register is addressed for the read operations (see table ii). 6 rdslt0 52/ 3 mode interface mode select bit. with this bit set to 0, interface mode 2 is enabled. with this bit set to 1, interface mode 1 is enabled where din is used as an output as well as an input. this bit is set to 0 by default after every read cycle; thus when using the two-wire interface mode, this bit needs to be set to 1 in every write cycle. 4 convst conversion start bit. a logic one in this bit position starts a single conversion, and this bit is automati- cally reset to 0 at the end of conversion. this bit may also be used in conjunction with system calibration (see calibration section.) 3 calmd calibration mode bit. a 0 here selects self-calibration, and a 1 sele cts a system calibration (see table iv). 2 calslt1 calibration selection bits and start calibration bit. these bits have two functions. 1 calslt0 with the stcal bit set to 1 the calslt1 and calslt0 bits determine the type of calibration per 0 stcal formed by the part (see table iv). the stcal bit is automatically reset to 0 at the end of calibration. with the stcal bit set to 0 the calslt1 and calslt0 bits are decoded to address the calibration register for read/wr ite of calibration coefficients (see section on the calibration registers for more details).
ad7858/ad7858l "((" table iii. channel selection sgl/ diff 0 0 0 0 ain 1 ain 2 0 0 0 1 ain 3 ain 4 0 0 1 0 ain 5 ain 6 0 0 1 1 ain 7 ain 8 0 1 0 0 ain 2 ain 1 0 1 0 1 ain 4 ain 3 0 1 1 0 ain 6 ain 5 0 1 1 1 ain 8 ain 7 1 0 0 0 ain 1 agnd 1 0 0 1 ain 3 agnd 1 0 1 0 ain 5 agnd 1 0 1 1 ain 7 agnd 1 1 0 0 ain 2 agnd 1 1 0 1 ain 4 agnd 1 1 1 0 ain 6 agnd 1 1 1 1 ain 8 agnd *ain(+) refers to the positive input seen by the ad7858/ad7858l sample and hold circuit, * ain( ) refers to the negative input seen by the ad7858/ad7858l sample and hold circuit. table iv. calibration selection calmd calslt1 calslt0 calibration type 000a full internal calibration is initiated where the internal dac is calibrated followed by the internal gain error, and finally the internal offset error is calibrated out. this is the default setting. 0 0 1 here the internal gain error is calibrated out followed by the internal offset error calibrated out. 0 1 0 this calibrates out the internal offset error only. 0 1 1 this calibrates out the internal gain error only. 100a full system calibration is initiated here where first the internal dac is calibrated followed by the system gain error, and finally the system offset error is calibrated out. 1 0 1 here the system gain error is calibrated out foll owed by the system offset error . 1 1 0 this calibrates out the system offset error only. 1 1 1 this calibrates out the system gain error only.
"(#" ad7858/ad7858l msb zero busy sgl/ diff ch2 ch1 ch0 pmgt1 pmgt0 rdslt1 rdslt0 2/ 3 mode x calmd calslt1 calslt0 stcal lsb status register bit function description bit mnemonic comment 15 zero this bit is always 0. 14 busy conversion/calibration busy bit. when this bit is 1, it indicates that there is a conversion or calibration in progress. when this bit is 0, there is no conversion or calibration in progress. 13 sgl/ diff these four bits indicate the channel selected for conversion (see table iii). 12 ch2 11 ch1 10 ch0 9 pmgt1 power management bits. these bits along with the sleep pin will indicate if the part is in a 8 pmgt0 power-down mode or not. see table vi for description. 7 rdslt1 both of these bits are alw ays 1, indicating it is the status register being read (see t able ii). 6 rdslt0 52/ 3 mode interface mode select bit. with this bit at 0, the device is in interface mode 2. with this bit at 1, the device is in interface mode 1. this bit is reset to 0 after every read cycle. 4x don t care bit. 3 calmd calibration mode bit. a 0 in this bit indicates a self-calibration is selected, and a 1 in this bit indicates a system calibration is selected (see table iv). 2 calslt1 calibration selection bits and start calibration bit. the stcal bit is read as a 1 if a 1 calslt0 calibration is in progress and as a 0 if there is no calibration in progress. the calslt1 and 0 stcal calslt0 bits indicate which of the calibration registers are addressed for reading and writing (see section on the calibration registers for more details). status register the arrangement of the status register is shown below. the status register is a read-only register and contains 16 bits of data . the status register is selected by first writing to the control register and putting two 1s in rdslt1 and rdslt0. the function of t he bits in the status register are described below. the power-up status of all bits is 0. start write to control register setting rdslt0 = rdslt1 = 1 read status register '5 '-
ad7858/ad7858l "($" calibration registers the ad7858/ad7858l has 10 calibration registers in all, eight for the dac, one for the offset, and one for gain. data can be wr itten to or read from all 10 calibration registers. in self- and system calibration the part automatically modifies the calibration r egisters; only if the user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers. addressing the calibration registers the calibration selection bits in the control register calslt1 and calslt0 determine which of the calibration registers are ad- dressed (see table v). the addressing applies to both the read and write operations for the calibration registers. the user sho uld not attempt to read from and write to the calibration registers at the same time. table v. calibration register addressing calslt1 calslt0 comment 0 0 this combination addresses the gain (1) , offset (1) and dac registers (8) . ten registers in total. 0 1 this combination addresses the gain (1) and offset (1) registers . two registers in total. 1 0 this combination addresses the offset register . one register in total. 1 1 this combination addresses the gain register . one register in total. writing to/reading from the calibration registers for writing to the calibration registers a write to the control register is required to set the calslt0 and calslt1 bits. for reading from the calibration registers a write to the control register is required to set the calslt0 and calslt1 bits, but also to set the rdslt1 and rdslt0 bits to 10 (this ad- dresses the calibration registers for reading). the calibration register pointer is reset on writing to the control register setting the calslt1 and calslt0 bits, or upon completion of all the calibration register write/read operations. when reset it points to the first calibration register in the selected write/read sequence. the calibration register pointer will point to the gain calibration register upon reset in all but one case, this case being where the offset calibration register is selected on its own (calslt1 = 1, calslt0 = 0). where more than one calibra- tion register is being accessed the calibration register pointer will be automatically incremented after each calibration register write/read operation. the order in which the 10 calibration registers are arranged is shown in figure 7. the user may abort at any time before all the calibration register write/read opera- tions are completed, and the next control register write opera- tion will reset the calibration register pointer. the flow chart in figure 8 shows the sequence for writing to the calibration regis- ters and figure 9 for reading. cal register address pointer gain register offset register dac 1st msb register dac 8th msb register . . . . . . . . . . . . . . . . . . . . . (1) (2) (3) (10) calibration registers calibration register address pointer position is determined by the number of calibration registers addressed and the number of read/write operations '. * when reading from the calibration registers there will always be two leading zeros for each of the registers. when operating in serial interface mode 1 the read operations to the calibration registers cannot be aborted. the full number of read operations must be completed (see section on serial interface mode 1 timing for more detail). start write to control register setting stcal = 0 and calslt1, calslt0 = 00, 01, 10, 11 cal register pointer is automatically reset write to cal register (addr1 = 1, addr0 = 0) cal register pointer is automatically incremented last register write operation or abort ? finished yes no '/ '3*
"(%" ad7858/ad7858l start write to control register setting stcal = 0, rdslt1 = 1, rdslt0 = 0, and calslt1, calslt0 = 00, 01, 10, 11 cal register pointer is automatically reset read cal register cal register pointer is automatically incremented last register read operation or abort ? finished yes no '
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adjusting the offset calibration register the offset calibration register contains 16 bits, two leading zeros, and 14 data bits. by changing the contents of the offset register different amounts of offset on the analog input signal can be compensated for. increasing the number in the offset calibration register compensates for negative offset on the analog input signal, and decreasing the number in the offset calibration regis- ter compensates for positive offset on the analog input signal. the default value of the offset calibration register is 0010 0000 0000 0000 approximately. this is not an exact value, but the value in the offset register should be close to this value. each of the 14 data bits in the offset register is binary weighted; the msb has a weighting of 5% of the reference voltage, the msb-1 has a weighting of 2.5%, the msb-2 has a weighting of 1.25%, and so on down to the lsb which has a weighting of 0.0006%. this gives a resolution of 0.0006% of v ref approximately. more accurately the resolution is (0.05 v ref )/2 13 volts = 0.015 mv, with a 2.5 v reference. the maximum offset that can be compensated for is 5% of the reference voltage, which equates to 125 mv with a 2.5 v reference and 250 mv with a 5 v reference. q. if a +20 mv offset is present in the analog input signal and the reference voltage is 2.5 v what code needs to be written to the offset register to compensate for the offset? a. 2.5 v reference implies that the resolution in the offset regis- ter is 5% 2.5 v/2 13 = 0.015 mv. +20 mv/0.015 mv = 1310.72; rounding to the nearest number gives 1311. in binary terms this is 0101 0001 1111. therefore, decrease the offset register by 0101 0001 1111. this method of compensating for offset in the analog input signal allows for fine tuning the offset compensation. if the offset on the analog input signal is known, there will be no need to apply the offset voltage to the analog input pins and do a system calibration. the offset compensation can take place in software. adjusting the gain calibration register the gain calibration register contains 16 bits, two leading 0s and 14 data bits. the data bits are binary weighted as in the offset calibration register. the gain register value is effectively multiplied by the analog input to scale the conversion result over the full range. increasing the gain register compensates for a smaller analog input range and decreasing the gain register compensates for a larger input range. the maximum analog input range that the gain register can compensate for is 1.025 times the reference voltage, and the minimum input range is 0.975 times the reference voltage.
ad7858/ad7858l "(&" circuit information the ad7858/ad7858l is a fast, 12-bit single supply a/d con- verter. the part requires an external 4 mhz/1.8 mhz master clock ( clkin), two c ref capacitors, a convst signal to start conversion, and power supply decoupling capacitors. the part provides the user with track/hold, on-chip reference, calibration features, a/d converter, and serial interface logic functions on a single chip. the a/d converter section of the ad78 58/ad7858l consists of a conventional successive-approximation converter based around a capacitor dac. the ad7858/ad7858l accepts an analog input range of 0 to +v dd where the reference can be tied to v dd . the reference input to the part is buffered on-chip. a major advantage of the ad7858/ad7858l is t hat a conversion can be initiated in software as well as applying a signal to the convst pin. another innovative feature of the ad7858/ ad7858l is self-calibration on power-up, which is initiated having a capacitor from the cal pin to agnd, to give superior dc accuracy. see automatic calibration on power-up section. the part is available in a 24-pin ssop package and this offers the user considerable space-saving advantages over alternative solutions. the ad7858l version typically consumes only 5.5 mw making it ideal for battery-powered applications. converter details the master clock for the part must be applied to the clkin pin. convers ion is initiated on the ad7858/ad7858l by pulsing the convst input or by writing to the control register and setting the convst bit to 1. on the rising edge of convst (or at the end of the control register write operation), the on- chip track/hold goes from track to hold mode. the falling edge of the clkin signal that follows the rising edge of the convst signal initiates the conversion, provided the rising edge of convst occurs at least 10 ns typically before t his clkin edge. the conversion cycle will take 16.5 clkin periods from this clkin falling edge. if the 10 ns setup time is not met, the conversion will take 17.5 clkin periods. the maximum speci- fied conversion time is 4.6 s for the ad7858 (18t clkin , clkin = 4 mhz) and 10 s for the ad7858l (18t clkin , clkin = 1.8 mhz). when a conversion is completed, the busy output goes low, and then the result of the conversion can be read by accessing the data through the serial interface. to obtain optimum performance from the part, the read opera- tion should not occur during the conversion or 400 ns prior to the next convst rising edge. however, the maximum throughput rates are achieved by reading/writing during conver- sion, and reading/writing during conversion is likely to degrade the signal to (noise + distortion) by only 0.5 dbs. the ad7858 can operate at throughput rates up to 200 khz, 100 khz for the ad7858l. for the ad7858 a conversion takes 18 clkin periods; 2 clkin periods are needed for the acquisition time giving a full cycle time of 5 s (= 200 khz, clkin = 4 mhz). for the ad7858l 100 khz throughput can be obtained as follows: the clkin and convst signals are arranged to give a conversion time of 16.5 clkin periods as described above, 1.5 clkin periods are allowed for the acquisition time. this gives a full cycle time of 10 s (=100 khz, clkin = 1.8 mhz). when using the software conversion start for maximum through- put the user must ensure the control register write operation extends beyond the falling edge of busy. the falling edge of busy resets the convst bit to 0 and allows it to be repro- grammed to 1 to start the next conversion. typical connection diagram figure 10 shows a typical connection diagram for the ad7858/ ad7858l. the agnd and the dgnd pins are connected together at the device for good noise suppression. the cal pin has a 0.01 f capacitor to enable an automatic self-calibration on power-up. the conversion result is output in a 16-bit word with four leading zeros followed by the msb of the 12-bit result. note that after the av dd and dv dd power-up the part will ch1 ch2 ch3 ch4 ch5 oscilloscope 4 leading zeros for adc data auto cal on power-up optional external reference ad780/ ref-192 4mhz/1.8mhz oscillator master clock input 0.1 f 0.1 f 10 f analog supply +3v to +5v 0v to 2.5v input 0.1 f 0.01 f dv dd 0.01 f 0.1 f internal/ external reference 200khz/100khz pulse generator conversion start input serial clock input frame sync input serial data input serial data output data generator pulse generator clkin sclk din dout dgnd agnd c ref2 c ref1 ain() ain(+) av dd dv dd ad7858/ ad7858l '(7 , *
"(5" ad7858/ad7858l require approximately 150 ms for the internal reference to settle and for the automatic calibration on power-up to be completed. for applications where power consumption is a major concern then the sleep pin can be connected to dgnd. see power- down section for more detail on low power applications. analog input the equivalent circuit of the analog input section is shown in figure 11. during the acquisition interval the switches are both in the track position and the ain(+) charges the 20 pf cap acitor through the 125 resistance. on the rising edge of convst switches sw1 and sw2 go into the hold position retaining charge on the 20 pf capacitor as a sample of the signal on ain(+). the ain( ) is connected to the 20 pf capacitor, and this unbalances the voltage at node a at the input of the com- parator. the capacitor dac adjusts during the remainder of the conversion cycle to restore the voltage at node a to the correct value. this action transfers a charge, representing the analog input signal, to the capacitor dac which in turn forms a digital representation of the analog input signal. the voltage on the ain( ) pin directly influences the charge transferred to the capacitor dac at the hold instant. if this voltage changes dur- ing the conversion period, the dac representation of the analog input voltage will be altered. therefore it is most important that the voltage on the ain( ) pin remains constant during the conver- sion period. furthermore it is recommended that the ain( ) pin is always connected to agnd or to a fixed dc voltage. acquisition time the track and hold amplifier enters its tracking mode on the falling edge of the busy signal. the time required for the track and hold amplifier to acquire an input signal will depend on how quickly the 20 pf input capacitance is charged. the acqui- sition time is calculated using the formula: t acq 9 ( r in 125 ) 20 pf where r in is the source impedance of the input signal, and 125 , 20 pf is the input r, c. hold capacitor dac comparator track node a sw2 hold track sw1 125 125 20pf c ref2 ain( e ) ain(+) '
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dc/ac applications for dc applications high source impedances are acceptable provided there is enough acquisition time between conversions to charge the 20 pf capacitor. the acquisition time can be calculated from the above formula for different source imped- ances. for example with r in = 5 k , the required acquisition time will be 922 ns. for ac applications, removing high frequency components from the analog input signal is recommended by use of an rc low- pass filter on the ain(+) pin as shown in figure 13. in applica- tions where harmonic distortion and signal to noise ratio are critical the analog input should be driven from a low impedance source. large source impedances will significantly affect the ac performance of the adc. this may necessitate the use of an input buffer amplifier. the choice of the op amp will be a func- tion of the particular application. when no amplifier is used to drive the analog input the source impedance should be limited to low values. the maximum source impedance will depend on the amount of total harmonic distortion (thd) that can be tolerated. the thd will increase as the source impedance increases and performance will de- grade. figure 12 shows a graph of the total harmonic distortion versus analog input signal frequency for different source imped- ances. with the setup as in figure 13, the thd is at the 90 db level. with a source impedance of 1 k and no capacitor on the ain(+) pin, the thd increases with frequency. input frequency e khz e 72 e 76 e 92 0 100 20 thd e db 40 60 e 80 e 84 e 88 80 thd vs. frequency for different source impedances r in = 1k r in = 50 , 10nf as in figure 13 '
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8 in a single supply application (both 3 v and 5 v), the v+ and v of the op amp can be taken directly from the supplies to the ad7858/ad7858l which eliminates the need for extra external power supplies. when operating with rail-to-rail inputs and outputs, at frequencies greater than 10 khz care must be taken in selecting the particular op amp for the application. in particu- lar for single supply applications the input amplifiers should be connected in a gain of 1 arrangement to get the optimum per- formance. figure 13 shows the arrangement for a single supply application with a 50 and 10 nf low-pass filter (cutoff fre- quency 320 khz) on the ain(+) pin. note that the 10 nf is a capacitor with good linearity to ensure good ac performance. recommended single supply op amps are the ad820 and the ad820-3 v. +3v to +5v 10k 10k 10k 10k 10 f 0.1 f 50 v+ v+ v ref to ain(+) of ad7858/ad7858l 10nf (npo) ad820 ad820-3v v in (0 to v ref ) '
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ad7858/ad7858l "(." input range the analog input range for the ad7858/ad7858l is 0 v to v ref . the ain( ) pin on the ad7858/ad7858l can be biased up above agnd, if required. the advantage of biasing the lower end of the analog input range away from agnd is that the user does not need to have the analog input swing all the way down to agnd. this has the advantage in true single- supply applications that the input amplifier does not need to swing all the way down to agnd. the upper end of the analog input range is shifted up by the same amount. care must be taken so that the bias applied does not shift the upper end of the analog input above the av dd supply. in the case where the reference is the supply, av dd , the ain( ) must be tied to agnd. ad7858/ ad7858l ain(+) ain( e ) track and hold amplifier dout straight binary format v in = 0 to v ref '
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transfer function for the ad7858/ad7858l input range the designed code tran- sitions occur midway between successive integer lsb values (i.e., 1/2 lsb, 3/2 lsbs, 5/2 lsbs . . . fs 3/2 lsbs). the output coding is straight binary with 1 lsb = fs/4096 = 3.3 v/ 4096 = 0.8 mv when v ref = 3.3 v. the ideal input/output transfer characteristic is shown in f igure 15. output code 111...111 111...110 111...101 111...100 000...011 000...010 000...001 000...000 1lsb = fs 4096 0v 1lsb +fs e 1lsb v in = (ain(+) e ain( e )), input voltage '
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reference section for specified performance, it is recommended that when using an external reference this reference should be between 2.3 v and the analog supply av dd . the connections for the relevant reference pins are shown in the typical connection diagrams. if the internal reference is being used, the ref in /ref out pin should have a 100 nf capacitor connected to agnd very close to the ref in /ref out pin. these connections are shown in figure 16. if the internal reference is required for use external to the adc, it should be buffered at the ref in /ref out pin and a 100 nf connected from this pin to agnd. the typical noise performance for the internal reference, with 5 v supplies, is 150 nv/ hz @ 1 khz and dc noise is 100 v p-p. 0.1 f 0.01 f 0.1 f 0.1 f 10 f 0.1 f ad7858/ ad7858l analog supply +3v to +5v av dd dv dd c ref1 c ref2 ref in /ref out '
(5 * 39

the other option is that the ref in /ref out pin be overdriven by connecting it to an external reference. this is possible due to the series resistance from the ref in /ref out pin to the internal reference. this external reference can have a range that includes av dd . when using av dd as the reference source, the 100 nf capacitor from the ref in /ref out pin to agnd should be as close as possible to the ref in /ref out pin, and also the c ref1 pin should be connected to av dd to keep this pin at the same level as the reference. the connections for this arrangement are shown in figure 17. when using av dd it may be necessary to add a resistor in series with the av dd supply. this will have the effect of filtering the noise associated with the av dd supply. 0.1 f 0.01 f 0.1 f 0.1 f 10 f 0.1 f ad7858/ ad7858l analog supply +3v to +5v av dd dv dd c ref1 c ref2 ref in /ref out '
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"(/" ad7858/ad7858l performance curves figure 18 shows a typical fft plot for the ad7858 at 200 khz sample rate and 10 khz input frequency. frequency e khz 0 e 20 e 120 0 100 20 snr e db 40 60 e 40 e 60 e 80 80 e 100 av dd = dv dd = 3.3v f sample = 200khz f in = 10khz snr = 72.04db thd = e 88.43db '
(/ '',: figure 19 shows the snr vs. frequency for different supplies and different external references. input frequency e khz 74 73 0 100 20 s(n+d) ratio e db 40 60 72 71 70 80 69 av dd = dv dd with 2.5v reference unless stated otherwise 5.0v supplies, with 5v reference 5.0v supplies 5.0v supplies, l version 3.3v supplies '
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8 figure 20 shows the power supply rejection ratio vs. fre- quency for the part. the power supply rejection ratio is de- fined as the ratio of the power in adc output at frequency f to the power of a full-scale sine wave. psrr (db) = 10 log (pf/pfs) pf = power at frequency f in adc output, pfs = power of a full-scale sine wave. here a 100 mv peak-to-peak sine wave is coupled onto the av dd supply while the digital supply is left unaltered. both the 3.3 v and 5.0 v supply performances are shown. input frequency e khz e 78 e 80 e 90 0 100 20 psrr e db 40 60 e 82 e 84 e 86 80 e 88 av dd = dv dd = 3.3v/5.0v, 100mvp-p sine wave on av dd 3.3v 5.0v '
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8 power-down options the ad7858 provides flexible power management to allow the user to achieve the best power performance for a given through- put rate. the power management options are selected by programming the power management bits, pmgt1 and pmgt0, in the control register and by use of the sleep pin. table vi summarizes the power-down options that are available and how they can be selected by using either software, hardware, or a combination of both. the ad7858 can be fully or partially powered down. when fully powered down, all the on-chip cir- cuitry is powered down and i dd is 1 a typ. if a partial power- down is selected, then all the on-chip circuitry except the reference is powered down and i dd is 400 a typ. the choice of full or par- tial power-down does not give any significant improvement in throughput with a power-down between conversions. this is discussed in the next section power-up times. however, a partial power-down does allow the on-chip reference to be used externally even though the rest of the ad7858 circuitry is pow- ered down. it also allows the ad7858 to be powered up faster after a long power-down period when using the on-chip refer- ence (see power-up times using on-chip reference). when using the sleep pin, the power management bits pmgt1 and pmgt0 should be set to zero (default status on power-up). bringing the sleep pin logic high ensures normal operation, and the part does not power down at any stage. this may be necessary if the part is being used at high throughput rates when it is not possible to power down between conversions. if the user wishes to power down between conversions at lower throughput rates (i.e. <100 ksps for the ad7858) to achieve better power performances, then the sleep pin should be tied logic low. if the power-down options are to be selected in software only, then the sleep pin should be tied logic high. by setting the power management bits pmgt1 and pmgt0 as shown in table vi, a full power-down, full power-up, full power- down between conversions, and a partial power-down be- tween conversions can be selected.
ad7858/ad7858l "(6" table vi. power management options pmgt1 pmgt0 sleep 000 full power-down if not calibrating or converting (default condition after power-on) 001 normal operation 01x normal operation (independent of the sleep pin) 10x full power-down 11x partial power-down if not converting a typical connection diagram for a low power application is shown in figure 21 (ad7858l is the low power version of the ad7858). auto power down after conversion auto cal on power-up optional external reference 1.8mhz oscillator master clock input 0.1 f 0.1 f 10 f analog supply +3v 0v to 2.5v input 0.1 f 0.01 f 0.01 f 0.1 f internal reference 100khz pulse generator conversion start input serial clock input serial data output clkin sclk din dout dgnd agnd
c ref2 c ref1 ain( e ) ain(+) av dd dv dd ad7858/ ad7858l low power c/ p current, i = 1.5ma typ serial data input ref in /ref out ref192 '
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power-up times using an external reference when the ad7858 is powered up, the part is powered up from one of two conditions. first, when the power supplies are ini- tially powered up and, secondly, when the part is powered up from either a hardware or software power-down (see last section). when av dd and dv dd are powered up, the ad7858 should be left idle for approximately 32 ms (4 mhz clk) to allow for the autocalibration if a 10 nf cap is placed on the cal pin, (see calibration section). during power-up the functionality of the sleep pin is disabled, i.e., the part will not power down until the end of the calibration if sleep is tied logic low. the auto- calibration on power-up can be disabled if the cal pin is tied to a logic high. if the autocalibration is disabled, then the user must take into account the time required by the ad7858 to power-up before a self-calibration is carried out. this power-up time is the time taken for the ad7858 to power up when power is first applied (300 s) typ) or the time it takes the external reference to settle to the 12-bit level whichever is the longer. the ad7858 powers up from a full hardware or software power-down in 5 s typ. this limits the throughput which the part is capable of to 104 ksps for the ad7858 operating with a 4 mhz clk and 66 ksps for the ad7858l with a 1.8 mhz clk when powering down between conversions. figure 22 shows how power-down between conversions is implemented using the convst pin. the user first selects the power-down between conversions option by using the sleep pin and the power management bits, pmgt1 and pmgt0, in the control register, (see last section). in this mode the ad7858 automati- cally enters a full power-down at the end of a conversion, i.e., when busy goes low. the falling edge of the next convst pulse causes the part to power up. assuming the external refer- ence is left powered up, the ad7858 should be ready for normal operation 5 s after this falling edge. the rising edge of convst initiates a conversion so the convst pulse should be at least 5 s wide. the part automatically powers down on completion of the conversion. 5 s t convert power-up time normal operation full power-down power-up time start conversion on rising edge power-up on falling edge busy '
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;9 ,39 convst y note: where the software convst is used or automatic full power-down, the part must be powered up in software with an extra write setting pmgt1 = 0 and pmgt0 = 1 before a con- version is initiated in the next write. automatic partial power- down after a calibration is not possible; the part must be powered down manually. if software calibrations are to be used when operating in the partial power-down mode, then three separate writes are required. the first initiates the type of cali- bration required, the second write powers the part down into partial power-down mode, while the third write powers the part up again before the next calibration command is issued. using the internal (on-chip) reference as in the case of an external reference, the ad7858 can power- up from one of two conditions, power-up after the supplies are connected or power-up from hardware/software power-down. when using the on-chip reference and powering up when av dd and dv dd are first connected, it is recommended that the power- up calibration mode be disabled as explained above. when using the on-chip reference, the power-up time is effectively the time it takes to charge up the external capacitor on the ref in /ref out pin. this time is given by the equation: t up = 9 r c where r 150 k and c = external capacitor.
"#7" ad7858/ad7858l the recommended value of the external capacitor is 100 nf; this gives a power-up time of approximately 135 ms before a calibration is initiated and normal operation should commence. when c ref is fully charged, the power-up time from a hardware or software power-down reduces to 5 s. this is because an internal switch opens to provide a high impedance discharge path for the reference capacitor during power-down see figure 23. an added advantage of the low charge leakage from the reference capacitor during power-down is that even though the reference is being powered down between conversions, the reference capacitor holds the reference voltage to within 0.5 lsbs with throughput rates of 100 samples/second and over with a full power-down between conversions. a high input impedance op amp like the ad707 should be used to buffer this reference capacitor if it is being used externally. note, if the ad7858 is left in its power-down state for more than 100 ms, the charge on c ref will start to leak away and the power-up time will increase. if this long power-up time is a problem, the user can use a partial power-down for the last conversion so the reference remains powered up. ad7858 ref in /ref out external capacitor switch opens during power-down buf on-chip reference to other circuitry '
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; power vs. throughput rate the main advantage of a full power-down after a conversion is that it significantly reduces the power consumption of the part at lower throughput rates. when using this mode of operation, the ad7858 is only powered up for the duration of the conver- sion. if the power-up time of the ad7858 is taken to be 5 s and it is assumed that the current during power-up is 4 ma typ, then power consumption as a function of throughput can easily be calculated. the ad7858 has a conversion time of 4.6 s with a 4 mhz external clock. this means the ad7858 con- sumes 4 ma typ, (or 12 mw typ v dd = 3 v) for 9.6 s in every conversion cycle if the device is powered down at the end of a conversion. if the throughput rate is 1 ksps, the cycle time is 1000 s and the average power dissipated during each cycle is (9.6/1000) (12 mw) = 115 w. the graph, figure 24, shows the power consumption of the ad7858 as a function of through- put. table vii lists the power consumption for various through- put rates. table vii. power consumption vs. throughput throughput rate power 1 ksps 115 w 10 ksps 1.15 mw power e mw 0.01 1 10 throughput e ksps 0 10 20 30 40 50 0.1 515253545 ad7858 (4mhz clk) ad7858l (1.8mhz clk) '
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calibration section calibration overview the automatic calibration that is performed on power-up en- sures that the calibration options covered in this section will not be required in a significant amount of applications. the user will not have to initiate a calibration unless the operating condi- tions change (clkin frequency, analog input mode, reference voltage, temperature, and supply voltages). the ad7858/ ad7858l have a number of calibration features that may be required in some applications and there are a number of advan- tages in performing these different types of calibration. first, the internal errors in the adc can be reduced significantly to give superior dc performance, and secondly, system offset and gain errors can be removed. this allows the user to remove reference errors (whether it be internal or external reference) and to make use of the full dynamic range of the ad7858/ ad7858l by adjusting the analog input range of the part for a specific system. there are two main calibration modes on the ad7858/ad7858l, self-calibration and system calibration. there are various op- tions in both self-calibration and system calibration as outlined previously in table iv. all the calibration functions can be initiated by pulsing the cal pin or by writing to the control register and setting the stcal bit to one. the timing diagrams that follow involve using the cal pin. the duration of each of the different types of calibrations is given in table viii for the ad7858 with a 4 mhz master clock. these calibration times are master clock dependent. therefore, the calibrating times for the ad7858l (clkin = 1.8 mhz) will be longer than those quoted in table viii. table viii. calibration times (ad7858 with 4 mhz clkin) type of self- or system calibration time full 31.25 ms offset + gain 6.94 ms offset 3.47 ms gain 3.47 ms
ad7858/ad7858l "#(" automatic calibration on power-on the cal pin has a 0.15 a pull-up current source connected to it internally to allow for an automatic full self-calibration on power-on. a full self-calibration will be initiated on power-on if a capacitor is c onnected from the cal pin to dgnd. the internal current source connected to the cal pin charges up the external capacitor and the time required to charge the exter- nal capacitor will depend on the size of the capacitor itself. this time should be large enough to ensure that the internal refer- ence is settled before the calibration is performed. a 33 nf capacitor is sufficient to ensure that the internal reference has settled (see power-up times) before a calibration is initiated taking into account trigger level and current source variations on the cal pin. however, if an external reference is being used, this reference must have stabilized before the automatic calibration is initiated (a larger capacitor on the cal pin should be used if the external reference has not settled when the autocalibration is initiated). once the capacitor on the cal pin has charged, the calibration will be performed which will take 32 ms (4 mhz clkin). therefore the autocalibration should be complete before operating the part. after calibration, the part is accurate to the 12-bit level and the specifications quoted on the data sheet apply. there will be no need to perform another calibration unless the operating conditions change or unless a system calibration is required. self-calibration description there are four different calibration options within the self- calibration mode. first, there is a full self-calibration where the dac, internal gain, and internal offset errors are calibrated out. then, there is the (gain + offset) self-calibration which cali- brates out the internal gain error and then the internal offset errors. the internal dac is not calibrated here. finally, there are the self-offset and self-gain calibrations which calibrate out the internal offset errors and the internal gain errors respectively. the internal capacitor dac is calibrated by trimming each of the capacitors in the dac. it is the ratio of these capacitors to each other that is critical, and so the calibration algorithm en- sures that this ratio is at a specific value by the end of the cali- bration routine. for the offset and gain there are two separate capacitors, one of which is trimmed when an offset or gain calibration is performed. again, it is the ratio of these capacitors to the capacitors in the dac that is critical and the calibration algorithm ensures that this ratio is at a specified value for both the offset and gain calibrations. the zero-scale error is adjusted for an offset calibration, and the positive full-scale error is adjusted for a gain calibration. self-calibration timing the diagram of figure 25 shows the timing for a full self- calibration. here the busy line stays high for the full length of the self-calibration. a self-calibration is initiated by bringing the cal pin low (which initiates an internal reset) and then high again or by writing to the control register and setting the stcal bit to 1 ( note that if the part is in a power-down mode the cal pulse- width must take account of the power-up time ). the busy line is triggered high from the rising edge of cal (or the end of the write to the control register if calibration is initiated in soft- ware), and busy will go low when the full self-calibration is complete after a time t cal as shown in figure 25. for the self- ( gain + offset), self-offset, and self-gain calibrations the busy line will be triggered high by the rising edge of the cal signal (or the end of the write to the control register if calibration is initiated in software) and will stay high for the full duration of the self-calibration. the length of time that the busy is high will depend on the type of self-calibration that is initiated. typical figures are given in table viii. the timing diagrams for the other self-calibration options will be similar to that outlined in figure 25. t 1 = 100ns min, t 15 = 2.5 t clkin max, t cal = 125013 t clkin t 1 t 15 t cal busy (o/p) (i/p) '
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system calibration description system calibration allows the user to take out system errors external to the ad7858/ad7858l as well as calibrate the errors of the ad7858/ad7858l itself. the maximum calibration range for the system offset errors is 5% of v ref and for the system gain errors is 2.5% of v ref . this means that the maxi- mum allowable system offset voltage applied between the ain(+) and ain( ) pins for the calibration to adjust out this error is 0.05 v ref ( i.e., the ain(+) can be 0.05 v ref above ain(? or 0.05 v ref below ain(? ). for the system gain error the maximum allowable system full-scale voltage that can be applied between ain(+) and ain( ) for the calibration to adjust out this error is v ref 0.025 v ref ( i.e., the ain(+) above ain(? ). if the system offset or system gain errors are outside the ranges mentioned the system calibration algorithm will reduce the errors as much as the trim range allows. figures 26 through 28 illustrate why a specific type of system calibration might be used. figure 26 shows a system offset calibration (assuming a positive offset) where the analog input range has been shifted upwards by the system offset after the system offset calibration is completed. a negative offset may also be accounted for by a system offset calibration. max system offset is 5% of v ref v ref e 1lsb sys offset agnd analog input range max system full scale is 2.5% from v ref system offset calibration max system offset is 5% of v ref sys offset agnd v ref + sys offset v ref e 1lsb analog input range '
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"##" ad7858/ad7858l figure 27 shows a system gain calibration (assuming a system full scale greater than the reference voltage) where the analog input range has been increased after the system gain calibration is completed. a system full-scale voltage less than the reference voltage may also be accounted for by a system gain calibration. max system full scale is 2.5% from v ref agnd sys f.s. v ref e 1lsb analog input range system gain calibration max system full scale is 2.5% from v ref agnd sys f.s. v ref e 1lsb analog input range '
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finally in figure 28 both the system offset and gain are ac- counted for by the a system offset followed by a system gain calibration. first the analog input range is shifted upwards by the positive system offset and then the analog input range is adjusted at the top end to account for the system full scale. max system offset is 5% of v ref v ref e 1lsb sys offset agnd analog input range system offset calibration followed by system gain calibration max system offset is 5% of v ref sys offset agnd sys f.s. v ref e 1lsb analog input range max system full scale is 2.5% from v ref v ref + sys offset max system full scale is 2.5% from v ref sys f.s. '
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system gain and offset interaction the inherent architecture of the ad7858/ad7858l leads to an interaction between the system offset and gain errors when a system calibration is performed. therefore, it is recommended to perform the cycle of a system offset calibration followed by a system gain calibration twice. separate system offset and system gain calibrations reduce the offset and gain errors to at least the 12-bit level. by performing a system offset cal first and a system gain calibration second, priority is given to reducing the gain error to zero before reducing the offset error to zero. if the system errors are small, a system offset calibration would be performed, followed by a system gain calibration. if the system errors are large (close to the specified limits of the calibration range), this cycle would be repeated twice to ensure that the offset and gain errors were reduced to at least the 12-bit level. the advantage of doing separate system offset and system gain calibrations is that the user has more control over when the analog inputs need to be at the required levels, and the convst signal does not have to be used. alternatively, a system (gain + offset) calibration can be performed. it is recommended to perform three system (gain + offset) calibrations to reduce the offset and gain errors to the 12-bit level. for the system (gain + offset) calibration priority is given to reducing the offset error to zero before reducing the gain error to zero. thus if the system errors are small then two system (gain + offset) calibrations will be sufficient. if the sys- tem errors are large (close to the specified limits of the calibra- tion range) three system (gain + offset) calibrations may be required to reduced the offset and gain errors to at least the 12- bit level. there will never be any need to perform more than three system (offset + gain) calibrations. the zero scale error is adjusted for an offset calibration and the positive full-scale error is adjusted for a gain calibration. system calibration timing the calibration timing diagram in figure 29 is for a full system calibration where the falling edge of cal initiates an internal reset before starting a calibration ( note that if the part is in power- down mode the cal pulsewidth must take account of the power-up time ). if a full system calibration is to be performed in software it is easier to perform separate gain and offset calibrations so that the convst bit in the control register does not have to be programmed in the middle of the system calibration sequence. the rising edge of cal starts calibration of the internal dac and causes the busy line to go high. if the control register is set for a full system calibration, the convst must be used also. the full-scale system voltage should be applied to the analog input pins from the start of calibration. the busy line will go low once the dac and system gain calibration are complete. next the system offset voltage is applied to the ain pin for a minimum setup time (t setup ) of 100 ns before the rising edge of the convst and remain until the busy signal goes low. the rising edge of the convst starts the system offset calibration section of the full system calibration and also causes the busy signal to go high. the busy signal will go low after a time t cal2 when the calibration sequence is com- plete. in some applications not all the input channels may be used. in this case it may be useful to dedicate two input chan- nels for the system calibration, one which has the system offset voltage applied to it, and one which has the system full scale voltage applied to it. when a system offset or gain calibration is performed, the channel selected should correspond to the sys- tem offset or system full-scale voltage channel. the timing for a system (gain + offset) calibration is very similar to that of figure 29 the only difference being that the time t cal1 will be replaced by a shorter time of the order of t cal2 as the internal dac will not be calibrated. the busy signal will signify when the gain calibration is finished and when the part is ready for the offset calibration. t 1 = 100ns min, t 14 = 50/90ns min 5v/3v, t 15 = 2.5 t clkin max, t cal1 = 111114 t clkin , t cal2 = 13899 t clkin t 1 t 15 t cal1 t cal2 t 16 t setup v system full scale v offset (i/p) busy (o/p) (i/p) ain (i/p) '
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ad7858/ad7858l "#$" the timing diagram for a system offset or system gain calibra- tion is shown in figure 30. here again the cal is pulsed and the rising edge of the cal initiates the calibration sequence (or the calibration can be initiated in software by writing to the control register). the rising edge of the cal causes the busy line to go high and it will stay high until the calibration se- quence is finished. the analog input should be set at the correct level for a m inimum setup time (t setup ) of 100 ns before the rising edge of cal and stay at the correct level until the busy signal goes low. (i/p) busy (o/p) t 1 ain (i/p) t 15 t setup t cal2 v system full scale or v system offset '
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serial interface summary table ix details the two interface modes and the serial clock edges from which the data is clocked out by the ad7858/ ad7858l (dout edge) and that the data is latched in on (din edge). in both interface modes 1 and 2 the sync is gated with the sclk. thus the sync o may clock out the msb of data. sub- sequent bits will be clocked out by the serial clock, sclk. the condition for the sync o clocking out the msb of data is as follows: the falling edge of sync will clock out the msb if the serial clock is low when the sync goes low. if this condition is not the case, the sclk will clock out the msb. if a noncontinuous sclk is used, it should idle high. table ix. sclk active edges interface mode edge dout edge din 1, 2 sclk sclk resetting the serial interface when writing to the part via the din line there is the possibility of writing data into the incorrect registers, such as the test regis- ter for instance, or writing the incorrect data and corrupting the serial interface. the sync pin acts as a reset. bringing the sync pin high resets the internal shift register. the first data bit after the next sync falling edge will now be the first bit of a new 16-bit transfer. it is also possible that the test register con- tents were altered when the interface was lost. therefore, once the serial interface is reset it may be necessary to write the 16-bit word 0100 0000 0000 0010 to restore the test register to its default value. now the part and serial interface are completely reset. it is always useful to retain the ability to program the sync line from a port of the controller/dsp to have the ability to reset the serial interface. table x summarizes the interface modes provided by the ad7858/ad7858l. it also outlines the various p/ c to which the particular interface is suited. interface mode 1 may only be set by programming the control register (see section on control register). some of the more popular processors, controllers, and the dsp machines that the ad7858/ad7858l will interface to directly are mentioned here. this does not cover all cs, ps, and dsps. a more detailed timing description on each of the interface modes follows. table x. interface mode description interface processor/ mode controller comment 1 8xc51 (2-wire) 8xl51 (din is an input/ pic17c42 output pin) 2 68hc11 (3-wire, spi) 68l11 (default mode) 68hc16 pic16c64 adsp21xx dsp56000 dsp56001 dsp56002 dsp56l002
"#%" ad7858/ad7858l detailed timing section mode 1 (2-wire 8051 interface) the read and writing takes place on the din line and the con- version is initiated by pulsing the convst pin (note that in every write cycle the 2/ 3 mode bit must be set to 1). the conversion may be started by setting the convst bit in the control register to 1 instead of using the convst pin. below in figure 31 and in figure 32 are the timing diagrams for operating mode 1 in t able x where we are in the 2-wire inter- face mode. here the din pin is used for both input and output as shown. the sync input is level triggered active low and can be pulsed (figure 31) or can be constantly low (figure 32). in figure 31 the part samples the input data on the rising edge of sclk. after the 16th rising edge of sclk the din is con- figured as an output. when the sync is taken high the din is three-stated. taking sync low disables the three-state on the din pin and the first sclk falling edge clocks out the first data bit. once the 16 clocks have been provided the din pin will automatically revert back to an input after a time, t 14 . note that a continuous sclk shown by the dotted waveform in figure 35 can be used provided that the sync is low for only 16 clock pulses in each of the read and write cycles. in figure 32 the sync line is tied low permanently and this results in a different timing arrangement. with sync tied low permanently the din pin will never be three-stated. the 16th rising edge of sclk configures the din pin as an input or an output as shown in the diagram. here no more than 16 sclk pulses must occur for each of the read and write operations. if reading from and writing to the calibration registers in this interface mode, all the selected calibration registers must be read from or written to. the read and write operations cannot be aborted. when reading from the calibration registers, the din pin will remain as an output for the full duration of all the calibration register read operations. when writing to the calibra- tion registers, the din pin will remain as an input for the full duration of all the calibration register write operations. t 3 = e 0.4 t sclk min (noncontinuous sclk) 0.4 t sclk ns min/max (continuous sclk), t 6 = 75/115ns max (5v/3v), t 7 = 40/60ns min (5v/3v), t 8 = 20/30ns min (5v/3v) polarity pin logic high (i/p) sclk (i/p) din (i/o) t 3 t 11 t 3 t 11 16 1 16 1 t 12 t 8 t 6 t 6 t 5 t 14 din becomes an output din becomes an input db15 db0 db15 db0 three-state data read data write t 7 '
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ad7858/ad7858l "#&" mode 2 (3-wire spi/qspi interface mode) this is the default interface mode. in figure 33 below we have the timing diagram for interface mode 2 which is the spi/qspi interface mode. here the sync input is active low and may be pulsed or tied permanently low. if sync is permanently low, 16 clock pulses must be applied to the sclk pin for the part to operate correctly, otherwise with a pulsed sync input a continuous sclk may be applied pro- vided sync is low for only 16 sclk cycles. in figure 33 the sync going low disables the three-state on the dout pin. the first falling edge of the sclk after the sync going low clocks out the first leading zero on the dout pin. the dout pin is three-stated again a time t 12 after the sync goes high. with the din pin the data input has to be set up a time t 7 be- fore the sclk rising edge as the part samples the input data on the sclk rising edge in this case. if resetting the interface is required, the sync must be taken high and then low. t 11 t 12 16 6 5 4 3 2 1 t 10 t 8 t 6 t 9 t 8 t 6 t 3 t 5 three-state three-state db0 db10 db11 db12 db13 db14 db15 db14 db13 db12 db11 db10 db0 (i/p) sclk (i/p) dout (o/p) din (i/p) polarity pin logic high t 3 = e 0.4 t sclk min (noncontinuous sclk) 0.4 t sclk ns min/max (continuous sclk), t 6 = 75/115ns max (5v/3v), t 7 = 40/60ns min (5v/3v), t 8 = 20/30ns min (5v/3v), t 11 = 30/50ns min (noncontinuous sclk) (5v/3v), (30/50)/0.4 t sclk ns min/max (continuous sclk) (5v/3v) db15 t 7 '
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"#5" ad7858/ad7858l configuring the ad7858/ad7858l the ad7858/ad7858l contains 14 on-chip registers which can be accessed via the serial interface. in the majority of applications it will not be necessary to access all of these registers. here the clkin signal is applied directly after power-on; the clkin signal must be present to allow the part to perform a calibration. this automatic calibration will be completed approxim ately 32 ms after the ad7858 has powered up (4 mhz clk). for accessing the on-chip registers it is necessary to write to the part. to change the channel from the default channel setting the user will be required to write to the part. to enable serial interface mode 1 the user must also write to the part. figure 34 and 35 outline flowcharts of how to configure the ad7858/ ad7858l serial interface modes 1 and 2 respectively. the continuous loops on all diagrams indicate the sequence for more than one conversion. the options of using a hardware (pulsing the convst pin) or software (setting the convst bit to 1) conversion start, and reading/writing during or after conversion are shown in figures 34 and 35. if the convst pin is never used then it should be tied to dv dd permanently. where refer- ence is made to the busy bit equal to a logic 0, to indicate the end of conversion, the user in this case would poll the busy bit in the status register. interface mode 1 configuration figure 34 shows the flowchart for configuring the part in inter- face mode 1. this mode of operation can only be enabled by writing to the control register and setting the 2/ 3 mode bit. reading and writing cannot take place simultaneously in this mode as the din pin is used for both reading and writing. initiate conversion in software ? start power-on, apply clkin signal, wait for automatic calibration apply (if required), sclk, write to control register setting channel and two-wire mode pulse pin wait for busy signal to go low or wait for busy bit = 0 no 1 serial interface mode ? apply (if required), sclk, write to control register setting channel two-wire mode read data during conversion ? no yes yes apply (if required), sclk, read current conversion result on din pin apply (if required), sclk, read previous conversion result on din pin wait approx. 200ns after rising edge or after end of control register write write to control register setting convst bit to 1 (see note) note: two separate writes are required to set a new channel address and initiate a conversion on that new channel in software as the acquisition time (2 t clkin ) must elapse before the conversion begins. if both commands are issued in the one write the result of this conversion should be discarded and the next conversion on that same channel will provide correct results. '
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ad7858/ad7858l "#." interface mode 2 configuration figure 35 shows the flowchart for configuring the part in inter- face mode 2. in this case the read and write operations take place simultaneously via the serial port. writing all 0s ensures that no valid data is written to any of the registers. when using the software conversion start and transferring data during con- version note 1 must be obeyed. apply (if required), sclk, write to control register setting channel, (see note 1) initiate conversion in software ? start power-on, apply clkin signal, wait for automatic calibration pulse pin wait for busy signal to go low or wait for busy bit = 0 no serial interface mode ? transfer data during conversion ? no yes yes apply (if required), sclk, read current conversion result on dout pin, and write channel selection notes 1 when using the software conversion start and transferring data during conversion the user must ensure the control register write operation extends beyond the falling edge of busy. the falling edge of busy resets the convst bit to 0 and only after thi s time can it be reprogrammed to 1 to start the next conversion. 2 two separate writes are required to set a new channel address and initiate a conversion on that new channel in software as the acquisition time (2 t clkin ) must elapse before the conversion begins. if both commands are issued in the one write the result of this conversion should be discarded and the next conversion on that same channel will provide correct results. wait approx 200ns after rising edge apply (if required), sclk, read previous conversion result on dout pin, and write channel selection no apply (if required), sclk, write to control register setting channel wait for busy signal to go low or wait for busy bit = 0 yes 2 write to control register setting convst bit to 1, read current conversion result on dout pin (see note 2) write to control register setting convst bit to 1, read previous result on dout pin (see notes 1&2) transfer data during conversion ? '
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"#/" ad7858/ad7858l microprocessor interfacing in many applications, the user may not require the facility of writing to most of the on-chip registers. the only writing neces- sary is to set the input channel configuration. after this the convst is applied, a conversion is performed, and the result may be read using the sclk to clock out the data from the output register on to the dout pin. at the same time a write operation occurs and this may consist of all 0s where no data is written to the part or may set a different input channel configu- ration for the next conversion. the sclk may be connected to the clkin pin if the user does not want to have to provide separate serial and master clocks. with this arrangement the sync signal must be low for 16 sclk cycles for the read and write operations. din dout clkin sclk ad7858/ ad7858l 4mhz/1.8mhz master clock signal to gate the sclk serial data output conversion start serial data input '
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ad7858/ad7858l to 8xc51 interface figure 37 shows the ad7858/ad7858l interface to the 8xc51. the 8xl51 is for interfacing to the ad7858/ad7858l when the supply is at 3 v. the 8xc51 only runs at 5 v. the 8xc51 is in mode 0 operation. this is a two-wire interface consisting of the sclk and the din which acts as a bidirec- tional line. the sync is tied low. the busy line can be used to give an interrupt driven system but this would not normally be the case with the 8xc51. for the 8xc51 12 mhz version the serial clock will run at a maximum of 1 mhz so the serial interface of the ad7858/ad7858l will only be running at 1 mhz. the clkin signal must be provided separately to the ad7858/ad7858l from a port line on the 8xc51 or from a source other than the 8xc51. here the sclk cannot be tied to the clkin as the sync is tied low permanently. the convst signal can be provided from an external timer or conversion can be started in software if required. the sequence of events would typically be to write to the control register via the din line setting a conversion start and the 2-wire interface mode (this would be performed in two 8-bit writes), wait for the conversion to be finished (4.6 s with 4 mhz clkin), read the conversion result data on the din line (this would be performed in two 8-bits reads), and repeat the sequence. the maximum serial frequency will be determined by the data access and hold times of the 8xc51 and the ad7858/ad7858l. 8xc51/l51 p3.0 p3.1 ad7858/ad7858l clkin sclk din optional 4mhz/1.8mhz busy (int0/p3.2) master slave optional '
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ad7858/ad7858l to 68hc11/16/l11/pic16c42 interface figure 38 shows the ad7858/ad7858l spi/qspi interface to the 68hc11/16/l11/pic16c42. the 68l11 is for interfacing to the ad7858/ad7858l when the supply is 3 v. the ad7858/ ad7858l is in interface mode 2. the sync line is not used and is tied to dgnd. the controller is configured as the mas- ter, by setting the mstr bit in the spcr to 1, and provides the serial clock on the sck pin. for all the controllers the cpol bit is set to 1 and for the 68hc11/16/l11 the cpha bit is set to 1. the clkin and convst signals can be supplied from the controller or from separate sources. the busy signal can be used as an interrupt to tell the controller when the conversion is finished, then the reading and writing can take place. if re- quired the reading and writing can take place during conversion and there will be no need for the busy signal in this case. 68hc11/l11/16 sck clkin sclk din optional 4mhz/1.8mhz busy master slave optional dout miso mosi spi dv dd hc16, qspi ad7858/ad7858l '
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for the 68hc16 the word length should be set to 16 bits, and the ss line should be tied to the sync pin for the qspi inter- face. the micro-sequencer and ram associated with the 68hc16 qspi port can be used to perform a number of read and write operations, and store the conversion results in memory, independent of the cpu. this is especially useful when reading the conversion results from all eight channels consecu- tively. the command section of the qspi port ram would be programmed to perform a conversion on one channel, read the conversion result, perform a conversion on the next channel, read the conversion result, and so on until all eight conversion results are stored into the qspi ram.
ad7858/ad7858l "#6" a typical sequence of events would be to write to the control register via the din line setting a conversion start and at the same time reading data from the previous conversion on the dout line (both the read and write operations would each be two 8-bit operations, one 16-bit operation for the 68hc16), wait for the conversion to be finished (= 4.6 s for ad7858 with 4 mhz clkin), and then repeat the sequence. the maxi- mum serial frequency will be determined by the data access and hold times of the controllers and the ad7858/ad7858l. ad7858/ad7858l to adsp-21xx interface figure 39 shows the ad7858/ad7858l interface to the adsp- 21xx. the adsp-21xx is the master and the ad7858/ad7 858l is the slave. the ad7858/ad7858l is in interface mode 2. for the adsp-21xx the bits in the serial port control register should be set up as tfsr = rfsr = 1 (need a frame sync for every tra nsfer), slen = 15 (16-bit word length), tfsw = rfsw = 1 (alternate framing mode for transmit and receive operations), invrfs = invtfs = 1 (active low rfs and tfs), irfs = 0, itfs = 1 (external rfs and internal tfs), and isclk = 1 (internal serial clock). the clkin and convst signals can be supplied from the adsp-21xx or from an external source. the serial clock from the adsp-21xx must be inverted before the sclk pin of the ad7858/ad7858l. this sclk could also be used to drive the clkin input of the ad7858/ad7858l. the busy signal indicates when the con- version is finished and may not be required. the data access and hold times of the adsp-21xx and the ad7858/ad7858l allow for a serial clock of 4 mhz/1.8 mhz at 5 v and 3.3 mhz/ 1.8 mhz at 3 v supplies. adsp-21xx clkin dout din optional 4mhz/1.8mhz busy master slave dt sck sclk dr optional ad7858/ad7858l '
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ad7858/ad7858l to dsp56000/1/2/l002 interface figure 40 shows the ad7858/ad7858l to dsp56000/1/2/ l002 interface. here the dsp5600x is the master and the ad7858 is the slave. the ad7858/ad7858l is in interface mode 2. the d sp56l002 is used when the ad7858/ad7858l is being operated at 3 v. the setting of the bits in the registers of the dsp5600x would be for synchronous operation (syn = 1), internal frame sync (scd2 = 1), gated internal clock (gck = 1, sckd = 1), 16-bit word length (wl1 = 1, wl0 = 0). since a gated clock is used here the sclk cannot be tied to the clkin of the ad7858/ ad7858l. the sclk from the dsp5600x must be inverted before it is applied to the ad7858/ad7858l. again the data access and hold times of the dsp5600x and the ad7858/ad7858l allows for a sclk of 4 mhz/1.8 mhz. dsp56000/1/2/l002 srd clkin sclk din optional busy master slave optional dout sc2 std sck 4mhz/1.8mhz ad7858/ad7858l '
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"$7" ad7858/ad7858l application hints grounding and layout the analog and digital supplies to the ad7858/ad7858l are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. the part has very good immunity to noise on the power supplies as can be seen by the psrr vs. frequency graph. however, care should still be taken with regard to grounding and layout. the printed circuit board that houses the ad7858/ad7858l should be designed such that the analog and digital sections are separated and confined to certain areas of the board. this facili- tates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes as it gives the best shielding. digital and analog ground planes should only be joined in one place. if the ad7858/ad7858l is the only device requiring an agnd to dgnd connection, then the ground planes should be connected at the agnd and dgnd pins of the ad7858/ad7858l. if the ad7858/ ad7858l is in a system where multiple devices require agnd to dgnd connections, the connection should still be made at one point only, a star ground point which should be established as close as possible to the ad7858/ad7858l. avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7858/ad7858l to avoid noise coupling. the power supply lines to the ad7858/ad7858l should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on oppo- site sides of the board should run at right angles to each other. this will reduce the effects of feedthrough through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with 10 f tantalum in parallel with 0.1 f ca- pacitors to agnd. all digital supplies should have a 0.1 f disc ceramic capacitor to agnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device, ideally right up against the device. in systems where a common supply voltage is used to drive both the av dd and dv dd of the ad7858/ad7858l, it is recom- mended that the system s av dd supply be used. in this case there should be a 10 resistor between the av dd pin and dv dd pin. this supply should have the recommended analog supply decoupling capacitors between the av dd pin of the ad7858/ad7858l and agnd and the recommended digital supply decoupling capacitor between the dv dd pin of the ad7858/ad7858l and dgnd. evaluating the ad7858/ad7858l performance the recommended layout for the ad7858/ad7858l is out- lined in the evaluation board for the ad7858/ad7858l. the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from the pc via the eval-control board. the eval-control board can be used in conjunction with the ad7858/ad7858l evaluation board, as well as many other analog devices evaluation boards ending in the cb desig- nator, to demonstrate/evaluate the ac and dc performance of the ad7858/ad7858l. the software allows the user to perform ac (fast fourier trans- form) and dc (histogram of codes) tests on the ad7858/ ad7858l. it also gives full access to all the ad7858/ad7858l on-chip registers allowing for various calibration and power- down options to be programmed. ad785x family all parts are 12 bits, 200 ksps, 3.0 v to 5.5 v. ad7853 single channel serial ad7854 single channel parallel ad7858 eight channel serial ad7859 eight channel parallel
ad7858/ad7858l "$(" page index topic page no. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . 1 product highlights . . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 timing specifications . . . . . . . . . . . . . . . . . . . . . . . 4 typical timing diagrams . . . . . . . . . . . . . . . . . . . . 5 absolute maximum ratings . . . . . . . . . . . . . . . . . 6 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin function descriptions . . . . . . . . . . . . . . . . . . 7 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 on-chip registers addressing the on-chip registers . . . . . . . . . . . . . . . . . . . 9 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 calibration registers . . . . . . . . . . . . . . . . . . . . . . 13 addressing the calibration registers . . . . . . . . . . . . . . . . 13 writing to/reading from the calibration registers . . . . . . 13 adjusting the offset calibration registers . . . . . . . . . . . . 14 adjusting the gain calibration register . . . . . . . . . . . . . . 14 circuit information . . . . . . . . . . . . . . . . . . . . . . . . 15 converter details . . . . . . . . . . . . . . . . . . . . . . . . . . 15 typical connection diagram . . . . . . . . . . . . . . 15 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 dc/ac applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 input range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 reference section . . . . . . . . . . . . . . . . . . . . . . . . . . 17 performance curves . . . . . . . . . . . . . . . . . . . . . . . . 18 power-down options . . . . . . . . . . . . . . . . . . . . . . . . 18 power-up times using an external reference . . . . . . . . . . . . . . . . . . . . . . 19 using the internal (on-chip) reference . . . . . . . . . . . . . 19 power vs. throughput rate . . . . . . . . . . . . . . . . 20 calibration section calibration overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 automatic calibration on power-on . . . . . . . . . . . . . . . . 21 self-calibration description . . . . . . . . . . . . . . . . . . . . . . . 21 self-calibration timing . . . . . . . . . . . . . . . . . . . . . . . . . . 21 system calibration description . . . . . . . . . . . . . . . . . . . . 21 system gain and offset interaction . . . . . . . . . . . . . . . . . 22 system calibration timing . . . . . . . . . . . . . . . . . . . . . . . 22 serial interface summary . . . . . . . . . . . . . . . . . . 23 resetting the serial interface . . . . . . . . . . . . . . . . . . . . . 23 detailed timing section mode 1 (2-wire 8051 interface) . . . . . . . . . . . . . . . . . . . 24 mode 2 (3-wire spi/qspi interface) . . . . . . . . . . . . . . . . 25 configuring the ad7858/ad7858l . . . . . . . . . . . . 26 interface mode 1 configuration . . . . . . . . . . . . . . . . . . . . 26 interface mode 2 configuration . . . . . . . . . . . . . . . . . . . . 27 microprocessor interfacing . . . . . . . . . . . . . . . 28 ad7858/ad7858l 8xc51 interface . . . . . . . . . . . . . . . 28 ad7858/ad7858l 68hc11/16/l11/pic16c42 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ad7858/ad7858l adsp-21xx interface . . . . . . . . . . . . 29 ad7858/ad7858l dsp56000/1/2/l002 interface . . . . . 29 application hints grounding and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 evaluating the ad7858/ad7858l performance . . . . . . . 30 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 32 table index # title page no. table i. write register addressing . . . . . . . . . . . . . . . . . 9 table ii. read register addressing . . . . . . . . . . . . . . . . . 9 table iii. channel selection . . . . . . . . . . . . . . . . . . . . . . 11 table iv. calibration selection . . . . . . . . . . . . . . . . . . . . 11 table v. calibration register addressing . . . . . . . . . . . 13 table vi. power management options . . . . . . . . . . . . . . 19 table vii. power consumption vs. throughput . . . . . . . 20 table viii. calibration times (ad7858 with 4 mhz clkin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table ix. sclk active edges . . . . . . . . . . . . . . . . . . . . . 23 table x. interface mode description . . . . . . . . . . . . . . . 23
"$#" ad7858/ad7858l outline dimensions dimensions shown in inches and (mm). 24-lead plastic dip (n-24) 24 112 13 0.260 0.001 (6.61 0.03) pin 1 1.228 (31.19) 1.226 (31.14) seating plane 0.02 (0.5) 0.016 (0.41) 0.07 (1.78) 0.05 (1.27) 0.32 (8.128) 0.30 (7.62) 0.011 (0.28) 0.009 (0.23) 0.130 (3.30) 0.128 (3.25) 0.11 (2.79) 0.09 (2.28) 15 0 notes 1. lead no. 1 identified by a dot or notch. 2. plastic leads will be either tin plated or solder dipped in accordance with mil-m-38510 requirements. 24-lead small outline package (r-24) 24 13 12 1 0.608 (15.45) 0.596 (15.13) 0.414 (10.52) 0.398 (10.10) 0.299 (7.6) 0.291 (7.39) pin 1 seating plane 0.01 (0.254) 0.006 (0.15) 0.019 (0.49) 0.014 (0.35) 0.096 (2.44) 0.089 (2.26) 0.05 (1.27) bsc 0.013 (0.32) 0.009 (0.23) 0.042 (1.067) 0.018 (0.447) 6 0 0.03 (0.76) 0.02 (0.51) notes 1. lead no. 1 identified by a dot. 2. soic leads will be either tin plated or solder dipped in a cco rdan c e with mil-m- 385 1 0 re qu irement s . 24-lead shrink small outline package (rs-24) 24 1 13 12 0.328 (8.33) 0.318 (8.08) 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.207) pin 1 seating plane 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) 0.0256 (0.65) bsc 0.015 (0.38) 0.010 (0.25) 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 0 notes 1. lead no. 1 identified by a dot. 2. leads will be either tin plated or solder dipped in accordance with mil-m-38510 requirements. *7($$."7"5077 :!,!9-

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